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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MC9S08QA4 Rev. 3, 1/2009
MC9S08QA4
8-Pin DFN Case 1452-02 8-Pin NB-SOIC Case 751-07
MC9S08QA4 Series
Covers: MC9S08QA4 MC9S08QA2
Features: * 8-bit HCS08 Central Processor Unit (CPU) - Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of -40C to 85C - HC08 instruction set with added BGND instruction - Support for up to 32 interrupt/reset sources * On-Chip Memory - Flash read/program/erase over full operating voltage and temperature - Random-access memory (RAM) - Security circuitry to prevent unauthorized access to RAM and flash contents * Power-Saving Modes - Two very low power stop modes - Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents - Very low power real time counter for use in run, wait, and stop modes with internal clock sources * Clock Source Options - Internal Clock Source (ICS) -- Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1 MHz to 10 MHz * System Protection - Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock - Low-voltage detection with reset or interrupt - Selectable trip points - Illegal opcode detection with reset - Illegal address detection with reset - Flash block protection * Development Support - Single-wire background debug interface
8-Pin PDIP Case 626-06
- Breakpoint capability to allow single breakpoint setting during in-circuit debugging * Peripherals - ADC -- 4-channel, 10-bit resolution; 1.7 mV/C temperature sensor; automatic compare function; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V - ACMP -- Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; output can be tied internally to TPM input capture - TPM -- One 1-channel timer/pulse-width modulator (TPM) module; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; ACMP output can be tied internally to input capture - MTIM -- 8-bit modulo timer module with 8-bit prescaler - KBI -- 4-pin keyboard interrupt module with software selectable polarity on edge or edge/level modes * Input/Output - Four GPIOs, one input-only pin and one output-only pin. - Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins except PTA5 * Package Options - 8-pin SOIC, PDIP, and DFN
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008-2009. All rights reserved.
Table of Contents
1 2 3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .5 3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .5 3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .6 3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .10 3.7 Internal Clock Source (ICS) Characteristics . . . . . . . . .11 3.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . . 3.9 Analog Comparator (ACMP) Electricals . . . . . . . . . . . 3.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 14 15 15 17 19 19
4 5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision 1 2 3
Date 1/2008 2/2008 1/2009 Initial public release
Description of Changes
Changed the designator of the device in Table 15. Changed the condition of Run supply current measured to fBus = 1 MHz in Table 7. Fixed the error of inconsistent table number.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08QA4RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 2 Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER MODULE (MTIM) PORT A TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/ADP3 PTA2/KBIP2/ADP2
The block diagram, Figure 1, shows the structure of the MC9S08QA4 MCU.
HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD
4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) ACMPO ACMP- ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16-BIT TIMER/PWM MODULE (TPM) TPMCH0
USER FLASH (MC9S08QA4 = 4096 BYTES) (MC9S08QA2 = 2048 BYTES)
ANALOG COMPARATOR (ACMP)
PTA1/KBIP1/ADP1/ACMP- PTA0/KBIP0/TPMCH0/ADP0/ACMP+
USER RAM (MC9S08QA4 = 256 BYTES) (MC9S08QA2 = 160BYTES) 16 MHz INTERNAL CLOCK SOURCE (ICS) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL
NOTES: 1 Port pins are software configurable with pullup device if input port. 2 Port pins are software configurable for output drive strength. 3 Port pins are software configurable for output slew rate control. 4 IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1). 5 RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). 6 PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). 7 When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device.
Figure 1. MC9S08QA4 Series Block Diagram
2
Pin Assignments
This section shows the pin assignments in the packages available for the MC9S08QA4 series.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 3
Pin Assignments
Table 1. Pin Sharing Priority
Priority PIN Lowest Port Pin PTA51 PTA4 Alt 1 IRQ Alt 2 TCLK ACMPO BKGD Alt 3 Highest Alt 4 RESET MS
VDD VSS
8-Pin 1 2 3 4 5 6 7 8
1
PTA3 PTA2 PTA1 PTA0
KBIP3 KBIP2 KBIP1 KBIP0
ADP3 ADP2 ADP12 TPMCH0 ADP02 ACMP-2 ACMP+2
Pin does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on the internally pulled-up RESET pin will not be pulled to VDD. The internal gates connected to this pin are pulled to VDD. 2 If ACMP and ADC are both enabled, both will have access to the pin.
PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS VDD VSS
1 2 3 4
8 7 6 5
PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/ADP1/ACMP- PTA2/KBIP2/ADP2 PTA3/KBIP3/ADP3
8-Pin PDIP/SOIC
PTA5/IRQ/TCLK/RESET 1 PTA4/ACMPO/BKGD/MS 2 VDD 3 VSS 4 8-Pin DFN
8 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 7 PTA1/KBIP1/ADP1/ACMP- 6 PTA2/KBIP2/ADP2 5 PTA3/KBIP3/ADP3
Figure 2. MC9S08QA4 Series in 8-Pin Packages
MC9S08QA4 Series MCU Data Sheet, Rev. 3 4 Freescale Semiconductor
Electrical Characteristics
3
3.1
Electrical Characteristics
Introduction
This chapter contains electrical and timing specifications for the MC9S08QA4 series of microcontrollers available at the time of publication.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 2 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Table 2. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value -0.3 to 3.8 120 -0.3 to VDD + 0.3 25 -55 to 150
Unit V mA V mA C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 5
Electrical Characteristics
Table 3. Thermal Characteristics
Rating Operating temperature range (packaged) Thermal resistance Single-layer board 8-pin PDIP 8-pin NB SOIC 8-pin DFN Thermal resistance Four-layer board 8-pin PDIP 8-pin NB SOIC 8-pin DFN JA 72 87 41 C/W JA 113 150 179 C/W Symbol TA Value TL to TH -40 to 85 Unit C
The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD x JA) where: -- -- -- -- -- TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user-determined Eqn. 1
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273C) Solving Equation 1 and Equation 2 for K gives: K = PD x (TA + 273C) + JA x (PD)2 Eqn. 3 Eqn. 2
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
3.4
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM).
MC9S08QA4 Series MCU Data Sheet, Rev. 3 6 Freescale Semiconductor
Electrical Characteristics
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 4. ESD and Latch-up Test Conditions
Model Human Body Description Series resistance Storage capacitance Number of pulses per pin Series resistance Machine Storage capacitance Number of pulses per pin Minimum input voltage limit Latch-up Maximum input voltage limit 7.5 V R1 C Symbol R1 C Value 1500 100 3 0 200 3 -2.5 V pF Unit pF
Table 5. ESD and Latch-Up Protection Characteristics
No. 1 2 3 4
1
Rating1 Human body model (HBM) Machine model (MM) Charge device model (CDM) Latch-up current at TA = 85C
Symbol VHBM VMM VCDM ILAT
Min 2000 200 500 100
Max -- -- -- --
Unit V V V mA
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.
3.5
DC Characteristics
Table 6. DC Characteristics (Temperature Range = -40 to 85C Ambient)
Parameter Symbol Min Typical Max Unit
This section includes information about power supply requirements and I/O pin characteristics.
Supply voltage (run, wait, and stop modes) (VDD falling) (VDD rising) Minimum RAM retention supply voltage applied to VDD Low-voltage detection threshold (VDD falling) (VDD rising) Low-voltage warning threshold (VDD falling) VLVW VLVD 1.80 1.88 2.08 1.82 1.90 2.1 1.91 V 1.99 2.2 V VRAM VDD 1.8 VLVDL (rising) Vpor1,2 -- -- -- 3.6 3.6 -- V V
MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 7
Electrical Characteristics
Table 6. DC Characteristics (Temperature Range = -40 to 85C Ambient) (continued)
Parameter (VDD rising) Power on reset (POR) re-arm voltage Bandgap voltage reference Input high voltage (VDD > 2.3 V) (all digital inputs) Input high voltage (1.8 V VDD 2.3 V) (all digital inputs) Input low voltage (VDD > 2.3 V) (all digital inputs) Input low voltage (1.8 V VDD 2.3 V) (all digital inputs) Input hysteresis (all digital inputs) Input leakage current (per pin) VIn = VDD or VSS, all input-only pins High impedance (off-state) leakage current (per pin) VIn = VDD or VSS, all input/output Internal pullup resistors3,4 Internal pulldown resistor (KBI) Output high voltage -- low drive (PTxDSn = 0) IOH = -2 mA (VDD 1.8 V) Output high voltage -- high drive (PTxDSn = 1) IOH = -10 mA (VDD 2.7 V) IOH = -6 mA (VDD 2.3 V) IOH = -3 mA (VDD 1.8 V) Maximum total IOH for all port pins Output low voltage -- low drive (PTxDSn = 0) IOL = 2.0 mA (VDD 1.8 V) Output low voltage -- high drive (PTxDSn = 1) IOL = 10.0 mA (VDD 2.7 V) IOL = 6 mA (VDD 2.3 V) IOL = 3 mA (VDD 1.8 V) Maximum total IOL for all port pins DC injection current 2, 5, 6, 7 VIn < VSS, VIn > VDD Single pin limit Total MCU limit, includes sum of all stressed pins Input capacitance (all non-supply pins)
1 2
Symbol
Min 2.16
Typical 2.19 1.4 1.20 -- -- -- -- -- 0.025 0.025 -- -- --
Max 2.27 -- 1.21 --
Unit
Vpor VBG VIH
-- 1.18 0.70 x VDD 0.85 x VDD --
V V V
-- 0.35 x VDD 0.30 x VDD -- 1.0 1.0 52.5 52.5 -- V V V A A k k
VIL Vhys |IIn| |IOZ| RPU RPD
-- 0.06 x VDD -- -- 17.5 17.5 VDD - 0.5
VOH VDD - 0.5 |IOHT| -- -- VOL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60 0.5
mA
V 0.5 0.5 0.5 60 mA
IOLT
IIC
-0.2 -5 --
-- -- --
0.2 5 7
mA mA pF
CIn
RAM will retain data down to POR voltage. RAM data not guaranteed to be valid following a POR. This parameter is characterized and not tested on each device. 3 Measurement condition for pull resistors: V = V In SS for pullup and VIn = VDD for pulldown. 4 PTA5/IRQ/TCLK/RESET pullup resistor may not pull up to the specified minimum V . However, all ports are functionally tested IH to guarantee that a logic 1 will be read on any port input when the pullup is enabled and no DC load is present on the pin. 5 All functional non-supply pins are internally clamped to V SS and VDD.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 8 Freescale Semiconductor
Electrical Characteristics
6
Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption).
40 PULLUP RESISTOR (k) 35 30 25 20
PULLUP RESISTOR TYPICALS PULLDOWN RESISTANCE (k)
85C 25C -40C
40 35 30 25 20
PULLDOWN RESISTOR TYPICALS
85C 25C -40C
1.8
2
2.2
2.4
2.6 2.8 VDD (V)
3
3.2
3.4
3.6
1.8
2.3
2.8 VDD (V)
3.3
3.6
Figure 3. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)
TYPICAL VOL VS IOL AT VDD = 3.0 V
85C 25C -40C
1.2 1 0.8 VOL (V) 0.6 0.4 0.2 0 0
0.2 0.15 VOL (V) 0.1 0.05 0
TYPICAL VOL VS VDD
85C, IOL = 2 mA 25C, IOL = 2 mA -40C, IOL = 2 mA
5
10 IOL (mA)
15
20
1
2
VDD (V)
3
4
Figure 4. Typical Low-Side Driver (Sink) Characteristics -- Low Drive (PTxDSn = 0)
TYPICAL VOL VS IOL AT VDD = 3.0 V
85C 25C -40C
1 0.8 0.6 VOL (V)
TYPICAL VOL VS VDD 0.4 0.3 VOL (V) 0.2 0.1 0 IOL = 3 mA 1 2 VDD (V) 3 4 IOL = 6 mA
85C 25C -40C
0.4 0.2 0 0 10 IOL (mA) 20 30
IOL = 10 mA
Figure 5. Typical Low-Side Driver (Sink) Characteristics -- High Drive (PTxDSn = 1)
MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 9
Electrical Characteristics
1.2 1 VDD - VOH (V) 0.8 0.6 0.4 0.2 0 0
TYPICAL VDD - VOH VS IOH AT VDD = 3.0 V
85C 25C -40C
0.25 0.2 VDD - VOH (V) 0.15 0.1 0.05 0
TYPICAL VDD - VOH VS VDD AT SPEC IOH
85C, IOH = 2 mA 25C, IOH = 2 mA -40C, IOH = 2 mA
-5
-10 IOH (mA))
-15
-20
1
2
VDD (V)
3
4
Figure 6. Typical High-Side (Source) Characteristics -- Low Drive (PTxDSn = 0)
0.4
0.8 TYPICAL VDD - VOH VS IOH AT VDD = 3.0 V 85C 25C -40C
TYPICAL VDD - VOH VS VDD AT SPEC IOH
85C 25C -40C
0.3 VDD - VOH (V) 0.2 0.1 0 1
VDD - VOH (V)
0.6 0.4 0.2 0 0
IOH = -10 mA IOH = -6 mA IOH = -3 mA 2 VDD (V) 3 4
-5
-10
-15 -20 IOH (mA)
-25
-30
Figure 7. Typical High-Side (Source) Characteristics -- High Drive (PTxDSn = 1)
3.6
Supply Current Characteristics
Table 7. Supply Current Characteristics
Parameter Symbol RIDD RIDD WIDD S1IDD S2IDD S3IDD -- -- VDD (V)1 3 2 3 2 3 3 2 3 2 3 2 3 2 3 2 Typical2 3.5 mA 2.6 mA 490 A 370 A 1 mA 475 nA 470 nA 600 nA 550 nA 750 nA 680 nA 300 nA 300 nA 70 A 60 A Max 5 mA -- 1 mA -- 1.5 mA 1.2 A -- 2 A -- 6 A -- -- -- -- -- T (C) 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
This section includes information about power supply current in various operating modes.
Run supply fBus = 8 MHz Run supply fBus = 1 MHz
current3 current3
measured in FBE mode at measured in FBE mode at
Wait mode supply current4 measured in FBE at 8 MHz Stop1 mode supply current Stop2 mode supply current Stop3 mode supply current RTI adder to stop1, stop2, or stop34 LVD adder to stop3 (LVDE = LVDSE = 1)4
MC9S08QA4 Series MCU Data Sheet, Rev. 3 10 Freescale Semiconductor
Electrical Characteristics
1 2
3 V values are 100% tested; 2 V values are characterized but not tested. Typicals are measured at 25 C. 3 Does not include any DC loads on port pins. 4 Most customers are expected to find that auto-wakeup from a stop mode can be used instead of the higher current wait mode.
3.7
Internal Clock Source (ICS) Characteristics
Table 8. ICS Specifications (Temperature Range = -40 to 85C Ambient)
Characteristic Symbol tIRST fint_ut fint_t fdco_ut fdco_t fdco_res_t Min -- 25 31.25 12.8 16 -- Typical1 60 32.7 -- 16.8 -- 0.1 Max 100 41.66 39.06 21.33 20 0.2 Unit s kHz kHz MHz MHz %fdco
Internal reference start-up time Average internal reference frequency -- untrimmed Average internal reference frequency -- trimmed DCO output frequency range -- untrimmed DCO output frequency range -- trimmed Resolution of trimmed DCO output frequency at fixed voltage and temperature2 Total deviation of DCO output from trimmed frequency2 At 8 MHz over full voltage and temperature range At 8 MHz and 3.6 V from 0 to 70 C FLL acquisition time 2,3 Long term jitter of DCO output clock (averaged over 2 ms interval)
1 2
fdco_t tAcquire CJitter
-- -- --
-1.0 to 0.5 0.5 -- 0.02
2 1 1.5 0.2
%fdco ms %fdco
Data in Typical column was characterized at 3.0 V, 25 C, or is typical recommended value. This parameter is characterized and not tested on each device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 11
Electrical Characteristics 0.250%
0.200%
0.150%
0.100% DEVIATION 0.050%
0.000%
-0.050% 1.6 2.1 2.6 VDD 3.1 3.6
Figure 8. Deviation of DCO Output from Trimmed Frequency (8 MHz, 25 C)
3.8
AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 12 Freescale Semiconductor
Electrical Characteristics
3.8.1
Control Timing
Table 9. Control Timing
Parameter Symbol fBus tRTI textrst Asynchronous path2 Synchronous path3 tILIH Min 0 700 100 100 1.5 tcyc 100 1.5 tcyc -- -- 500 Typical1 -- 1000 -- -- Max 10 1300 -- -- Unit MHz s ns ns
Bus frequency (tcyc = 1/fBus) Real-time interrupt internal oscillator period (see Table 9) External reset pulse width IRQ pulse width
2
KBIPx pulse width Asynchronous path2 Synchronous path3 Port rise and fall time (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes5
1 2
tILIH, tIHIL
--
--
ns
tRise, tFall tMSSU tMSH
3 30 --
-- -- --
ns ns s
100
--
--
Data in Typical column was characterized at 3.0 V, 25C. This is the shortest pulse that is guaranteed to be recognized. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40C to 85C. 5 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD.
1600 1400 1200 1000 Period (s) 800 600 400 200 0 -40 -40 0 20 40 Temperature (C) 60 80 100 = +3 = Mean = -3
Figure 9. Typical RTI Clock Period vs. Temperature
MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 13
Electrical Characteristics
textrst RESET PIN
Figure 10. Reset Timing
tIHIL KBIPx
IRQ/KBIPx tILIH
Figure 11. IRQ/KBIPx Timing
3.8.2
TPM/MTIM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 10. TPM/MTIM Input Timing
Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min 0 4 1.5 1.5 1.5 Max fBus/4 -- -- -- -- Unit Hz tcyc tcyc tcyc tcyc
tTCLK tclkh
TCLK tclkl
Figure 12. Timer External Clock
MC9S08QA4 Series MCU Data Sheet, Rev. 3 14 Freescale Semiconductor
Electrical Characteristics
tICPW TPMCHn
TPMCHn tICPW
Figure 13. Timer Input Capture Pulse
3.9
Analog Comparator (ACMP) Electricals
Table 11. Analog Comparator Electrical Specifications
Characteristic Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT Min 1.80 -- VSS - 0.3 -- 3.0 -- -- Typical -- 20 -- 20 9.0 -- -- Max 3.60 -- VDD 40 15.0 1.0 1.0 Unit V A V mV mV A s
3.10
ADC Characteristics
Table 12. 3 V 10-Bit ADC Operating Conditions
Conditions Absolute Symbol VDD VADIN CADIN RADIN 10 bit mode fADCK > 4 MHz fADCK < 4 MHz 8 bit mode (all valid fADCK) Min 1.8 VSS -- -- -- -- -- 0.4 fADCK 0.4 Typical1 -- -- 4.5 5 -- -- -- -- -- Max 3.6 VDD 5.5 7 5 10 10 8.0 MHz 4.0 Unit V V pF k Comment
Characteristic Supply voltage Input voltage Input capacitance Input resistance Analog source resistance
RAS
k
External to MCU
ADC conversion clock frequency
1
High Speed (ADLPC=0) Low Power (ADLPC=1)
Typical values assume VDD = 3.0 V, Temp = 25C, fADCK =1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 15
Electrical Characteristics
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+ -
+ -
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 14. ADC Input Impedance Equivalency Diagram Table 13. 3 V 10-Bit ADC Characteristics
Characteristic Supply current ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 ADC asynchronous clock source High speed (ADLPC=0) Low power (ADLPC=1) fADACK Conditions Symbol Min Typical1 Max Unit Comment
IDDAD
--
120
--
A
IDDAD
--
202
--
A
IDDAD
--
288
--
A
IDDAD
--
532
646
A
2 1.25
3.3 2
5 MHz 3.3
tADACK = 1/fADACK
MC9S08QA4 Series MCU Data Sheet, Rev. 3 16 Freescale Semiconductor
Electrical Characteristics
Table 13. 3 V 10-Bit ADC Characteristics (continued)
Characteristic Conversion time (including sample time) Conditions Short sample (ADLSMP=0) Long sample (ADLSMP=1) Short sample (ADLSMP=0) Sample time Long sample (ADLSMP=1) 10-bit mode Total unadjusted error 8-bit mode 10-bit mode Differential non-linearity DNL 8-bit mode 10-bit mode Integral non-linearity 8-bit mode 10-bit mode Zero-scale error 8-bit mode 10-bit mode Full-scale error 8-bit mode 10-bit mode Quantization error 8-bit mode 10-bit mode Input leakage error 8-bit mode Temp sensor slope Temp sensor voltage
1
Symbol
Min --
Typical1 20 40 3.5 23.5 1.5 0.7 0.5 0.3 0.5 0.3 1.5 0.5 1.0 0.5 -- -- 0.2 0.1 1.646 1.769 701.2
Max -- -- -- -- 3.5 1.5 1.0 0.5 1.0 0.5 2.1 0.7 1.5 0.5 0.5 0.5 4 1.2 --
Unit ADCK cycles
Comment See MC9S08QA4 Series Reference Manual for conversion time variances Includes quantization Monotonicity and no missing codes guaranteed
tADC
-- --
tADS
-- --
ADCK cycles
ETUE
LSB2
-- -- -- --
LSB2
INL -- -- EZS -- 0 EFS 0 -- EQ -- 0 EIL 0 -- m 25C - 85C 25C VTEMP25 -- --
LSB2
LSB2
VADIN = VSS
LSB2
VADIN = VDD
LSB2 Pad leakage3 * RAS
LSB2
-40C - 25C
mV/C -- -- mV
Typical values assume VDD = 3.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2 3 Based on input pad leakage current. Refer to pad electricals.
3.11
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 17
Electrical Characteristics
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see MC9S08QA4 Series Reference Manual. Table 14. Flash Characteristics
Characteristic Supply voltage for program/erase -40C to 85C Supply voltage for read operation Internal FCLK frequency
1
Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass
Min 1.8 1.8 150 5
Typical -- -- -- -- 9 4 4000 20,000
Max 3.6 3.6 200 6.67
Unit V V kHz s tFcyc tFcyc tFcyc tFcyc
Internal FCLK period (1/FCLK) Byte program time (random
2
location)2
2
Byte program time (burst mode) Page erase time Mass erase time2 endurance3
Program/erase TL to TH = -40C to + 85C T = 25C Data retention4
1 2
10,000 tD_ret 15
-- 100,000 100
-- -- --
cycles years
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Motorola defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 18 Freescale Semiconductor
Ordering Information
4
Ordering Information
Table 15. Device Numbering System
Memory Device Number Flash MC9S08QA4 MC9S08QA2 4 KB 2 KB RAM 256 bytes 160 bytes Type 8 DFN 8 PDIP 8 NB SOIC Designator FQ PA DN Document No. 98ARL10557D 98ASB42420B 98ASB42564B Package
This section contains ordering numbers for MC9S08QA4 series devices. See below for an example of the device numbering system.
MC 9 S08 QA 4 C XX E Status (MC = Fully qualified) Memory (9 = Flash-based) Core Family RoHS compliance indicator (E = yes) Package designator (see Table 15) Temperature range (C = -40C to 85C) Memory size (in KB)
5
* * *
Mechanical Drawings
8-pin DFN (plastic dual in-line pin) 8-pin NB SOIC (narrow body small outline integrated circuit) 8-pin PDIP (plastic dual in-line pin)
The following pages contain mechanical specifications for MC9S08QA4 series package options.
MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 19
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Document Number: MC9S08QA4 Rev. 3 1/2009

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